A device for power efficient networking may include a processor circuit configured to identify a time to enter a low power state. The processor circuit may be further configured to transmit, prior to the identified time, transmission parameters to a network coordinator device for a network of devices, the transmission parameters being associated with a transmission from at least one of the devices to the device. The processor circuit may be further configured to enter the low power state at the identified time. The processor circuit may be further configured to, upon exiting the low power state, receive the transmission from at least one of the devices based at least in part on the transmission parameters. The processor circuit may be further configured to receive the transmission without participating in a node admission process after exiting the low power state.