Invention Grant
- Patent Title: Pattern formation method, control device, and semiconductor device manufacture method
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Application No.: US14848075Application Date: 2015-09-08
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Publication No.: US10241394B2Publication Date: 2019-03-26
- Inventor: Keiko Morishita , Shingo Kanamitsu , Hideaki Sakurai
- Applicant: TOSHIBA MEMORY CORPORATION
- Applicant Address: JP Tokyo
- Assignee: Toshiba Memory Corporation
- Current Assignee: Toshiba Memory Corporation
- Current Assignee Address: JP Tokyo
- Agency: Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- Priority: JP2015-042769 20150304
- Main IPC: G03F1/72
- IPC: G03F1/72 ; G03F1/74 ; G03F1/80
Abstract:
In a pattern formation method according to an embodiment, a resist pattern is formed on a first film formed on a substrate. In the process for forming the resist pattern, the resist pattern includes a first pattern including a defect in a predetermined region on the first film. Next, a second film is accumulated on the first pattern in the predetermined region. Furthermore, a second pattern is formed in the first film with the resist pattern and the second film. Then, a third pattern is formed in the predetermined region on the first film.
Public/Granted literature
- US20160259240A1 PATTERN FORMATION METHOD, CONTROL DEVICE, AND SEMICONDUCTOR DEVICE MANUFACTURE METHOD Public/Granted day:2016-09-08
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