• Patent Title: Techniques for organizing three-dimensional array data
  • Application No.: US14129940
    Application Date: 2013-05-23
  • Publication No.: US10241707B2
    Publication Date: 2019-03-26
  • Inventor: Alex M. Wells
  • Applicant: Intel Corporation
  • Applicant Address: US CA Santa Clara
  • Assignee: INTEL CORPORATION
  • Current Assignee: INTEL CORPORATION
  • Current Assignee Address: US CA Santa Clara
  • International Application: PCT/US2013/042375 WO 20130523
  • International Announcement: WO2014/189511 WO 20141127
  • Main IPC: G06F3/06
  • IPC: G06F3/06
Techniques for organizing three-dimensional array data
Abstract:
Various embodiments are generally directed to storing data of a three-dimensional (3D) array in a tiled manner in which adjacent rows of adjacent planes are interleaved to enable more efficient retrieval in performing 3D stencil calculations. An apparatus to perform a stencil calculation includes a processor component, a storage communicatively coupled to the processor component, and an interleaving component for execution by the processor component to interleave storage of data of cells of adjacent rows of a first plane with data of cells of adjacent rows of an adjacent second plane of a 3D array among contiguous storage locations of the storage. Other embodiments are described and claimed.
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