Invention Grant
- Patent Title: Test key structure and method of measuring resistance of vias
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Application No.: US15369905Application Date: 2016-12-06
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Publication No.: US10247774B2Publication Date: 2019-04-02
- Inventor: Hsin-Hsien Chen , Sheng-Yuan Hsueh , Yi-Chung Sheng , Wen-Kai Lin , Chih-Kai Kang
- Applicant: UNITED MICROELECTRONICS CORP.
- Applicant Address: TW Hsin-Chu
- Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee Address: TW Hsin-Chu
- Agent Winston Hsu
- Main IPC: G01R31/28
- IPC: G01R31/28 ; H01L21/66

Abstract:
The present invention provides a test key structure for measuring or simulating a target via array. The structure includes a substrate with a test region, a plurality of first conductive lines in the test region; a plurality of second conductive lines in the test region and on the first conductive lines, wherein the first conductive lines and the second conductive lines overlaps vertically in a plurality of target regions, and a plurality of vias disposed between the first conductive lines and the second conductive lines, wherein at least two vias vertically contact one of the first conductive lines and one of the second conductive lines. The present invention further provides a method of measuring resistance by using the testkey structure.
Public/Granted literature
- US20180156862A1 TEST KEY STRUCTURE AND METHOD OF MEASURING RESISTANCE OF VIAS Public/Granted day:2018-06-07
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