Invention Grant
- Patent Title: Template-based methodology for validating hardware features
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Application No.: US15362902Application Date: 2016-11-29
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Publication No.: US10248534B2Publication Date: 2019-04-02
- Inventor: Purushotam Bheemanna , Niraj K. Pandey
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent David B. Woycechowsky
- Main IPC: G06F11/36
- IPC: G06F11/36 ; G06F11/34 ; G06F9/46 ; G06F11/263 ; G06F11/30 ; G06F9/48

Abstract:
In one embodiment of the present invention, a thread is scheduled for execution by a processor, and the thread includes instructions for testing functionality of a feature of the processor. A workload location on the thread is determined. A hook is placed on the determined workload location. The thread is executed by the processor. In response to encountering the hook during the execution of the thread, a workload is selected from a pool, and the pool includes two or more workloads.
Public/Granted literature
- US20180150319A1 TEMPLATE-BASED METHODOLOGY FOR VALIDATING HARDWARE FEATURES Public/Granted day:2018-05-31
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