Invention Grant
- Patent Title: System and method for filtering field programmable gate array input/output
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Application No.: US15182005Application Date: 2016-06-14
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Publication No.: US10248585B2Publication Date: 2019-04-02
- Inventor: Xianda Ma , Michael David Derbish , Cornelia Luise Edeltraut Koch-Stoschek , Rambabu Lolabattu , Simon yiu hoi Poon , Cheng Yang
- Applicant: Oracle International Corporation
- Applicant Address: US CA Redwood City
- Assignee: Oracle International Corporation
- Current Assignee: Oracle International Corporation
- Current Assignee Address: US CA Redwood City
- Agency: Kilpatrick Townsend & Stockton LLP
- Main IPC: G06F13/16
- IPC: G06F13/16 ; G06F13/42 ; H03K19/177

Abstract:
Systems and methods for adding a logic layer between FPGA I/O and the core logic of the FPGA. With the extra layer, users can monitor and/or modify the I/O to the FPGA. In addition, users can monitor and/or modify input/output to the core logics of the FPGA, thereby filtering both I/O to the FPGA and the logic blocks of the FPGA. With the filtering in place, a non-intrusive digital scope can be implemented which can, in turn, be used to create a “black box” regarding FPGA I/O during the occurrence of the catastrophic events within the system.
Public/Granted literature
- US20170357603A1 SYSTEM AND METHOD FOR FILTERING FIELD PROGRAMMABLE GATE ARRAY INPUT/OUTPUT Public/Granted day:2017-12-14
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