A timing controller may reduce power consumption and/or reduce influence on wireless communication. A line memory is capable of retaining at least pixel data of one line. An input interface circuit is used for receiving pixel data and storing the pixel data in the line memory. A frequency synthesizer is used for receiving the external pixel clock CKP received by the input interface circuit and generating an internal pixel clock CKINT having frequency being a coefficient K multiplied by frequency of the external pixel clock CKP. An image processing circuit is used for processing the pixel data stored in the line memory synchronously with the internal pixel clock CKINT.