Invention Grant
- Patent Title: Apparatuses and methods for generating a voltage in a memory
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Application No.: US15663545Application Date: 2017-07-28
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Publication No.: US10249348B2Publication Date: 2019-04-02
- Inventor: Hitoshi Tanaka , Yasunori Orito
- Applicant: MICRON TECHNOLOGY, INC.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Dorsey & Whitney LLP
- Main IPC: G11C5/14
- IPC: G11C5/14 ; G05F3/26 ; G05F3/16 ; G05F1/46 ; G05F1/10

Abstract:
Apparatuses and methods for generating a voltage are described. An example apparatus includes first, second, and third bias circuits configured to provide first, second, and third bias signals, respectively. The example apparatus further includes a voltage output circuit configured to receive the first, second, and third bias signals. The voltage output circuit includes an output circuit and a current circuit. The output circuit includes an output node, a first node, and an input circuit configured to receive the first bias signal. The output circuit is configured to provide an output voltage at the output node having a magnitude based on the magnitude of the first bias signal. The current circuit includes a first transistor configured to receive the second bias signal and further includes a second transistor configured to receive the third bias signal. The first transistor and second transistor are coupled in parallel and to the first node.
Public/Granted literature
- US20190035434A1 APPARATUSES AND METHODS FOR GENERATING A VOLTAGE IN A MEMORY Public/Granted day:2019-01-31
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