Invention Grant
- Patent Title: Stacked-type solid electrolytic capacitor package structure and method of manufacturing the same
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Application No.: US15644901Application Date: 2017-07-10
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Publication No.: US10249446B2Publication Date: 2019-04-02
- Inventor: Chien-Wei Lin , Shang-Che Lan , Ming-Tsung Chen
- Applicant: APAQ TECHNOLOGY CO., LTD.
- Applicant Address: TW Miaoli County
- Assignee: APAQ TECHNOLOGY CO., LTD.
- Current Assignee: APAQ TECHNOLOGY CO., LTD.
- Current Assignee Address: TW Miaoli County
- Agency: Li & Cai Intellectual Property (USA) Office
- Priority: TW105133289A 20161014
- Main IPC: H01G9/012
- IPC: H01G9/012 ; H01G9/15 ; H01G9/26 ; H01G9/10 ; H01G9/00 ; H01G9/08

Abstract:
The present disclosure provides a stacked-type solid electrolytic capacitor package structure and a method of manufacturing the same. The capacitor package structure includes a capacitor unit, a solder unit, a package unit and a conductive unit. The capacitor unit includes a plurality of first stacked capacitors. Each first stacked capacitor includes a first positive portion and a first negative portion. The first positive portion has at least one first through hole. The first through holes of the first positive portions are in communication with each other to form a first communication hole. The solder unit includes a first connection solder for filling the first communication hole so as to connect the first positive portions with each other. The package unit includes a package body for enclosing the capacitor unit and the solder unit. The conductive unit includes a first conductive terminal and a second conductive terminal.
Public/Granted literature
- US20180108493A1 STACKED-TYPE SOLID ELECTROLYTIC CAPACITOR PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME Public/Granted day:2018-04-19
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