Invention Grant
- Patent Title: Overlay and semiconductor process control using a wafer geometry metric
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Application No.: US15135022Application Date: 2016-04-21
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Publication No.: US10249523B2Publication Date: 2019-04-02
- Inventor: Pradeep Vukkadala , Sathish Veeraraghavan , Jaydeep K. Sinha
- Applicant: KLA-Tencor Corporation
- Applicant Address: US CA Milpitas
- Assignee: KLA-Tencor Corporation
- Current Assignee: KLA-Tencor Corporation
- Current Assignee Address: US CA Milpitas
- Agency: Suiter Swantz pc llo
- Main IPC: G01B9/02
- IPC: G01B9/02 ; G03F7/20 ; G01B11/16 ; G01B11/24 ; G01B11/27 ; H01L21/66 ; H01L21/67

Abstract:
The present invention may include acquiring a wafer shape value at a plurality of points of a wafer surface at a first and second process level, generating a wafer shape change value at each of the points, generating a set of slope of shape change values at each of the points, calculating a set of process tool correctables utilizing the generated set of slope of shape change values, generating a set of slope shape change residuals (SSCRs) by calculating a slope of shape change residual value at each of the points utilizing the set of process tool correctables, defining a plurality of metric analysis regions distributed across the surface, and then generating one or more residual slope shape change metrics for each metric analysis region based on one or more SSCRs within each metric analysis region.
Public/Granted literature
- US20160372353A1 Overlay and Semiconductor Process Control Using a Wafer Geometry Metric Public/Granted day:2016-12-22
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