Invention Grant
- Patent Title: Integrated circuit and manufacturing method thereof
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Application No.: US15681419Application Date: 2017-08-20
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Publication No.: US10249528B2Publication Date: 2019-04-02
- Inventor: Chiu-Jung Chiu , Hung-Chan Lin , Yu-Chun Chen
- Applicant: UNITED MICROELECTRONICS CORP.
- Applicant Address: TW Hsin-Chu
- Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee Address: TW Hsin-Chu
- Agent Winston Hsu
- Priority: CN201710628490 20170728
- Main IPC: H01L21/762
- IPC: H01L21/762 ; H01L21/02 ; H01L27/06 ; H01L21/768 ; H01L29/94 ; H01L49/02 ; H01L21/8234 ; H01L21/28

Abstract:
An integrated circuit includes a first insulation layer, a bottom plate, a first patterned dielectric layer, a medium plate, a second patterned dielectric layer, and a top plate. The first patterned dielectric layer is disposed on the bottom plate. The medium plate is disposed on the first patterned dielectric layer. At least a part of the first patterned dielectric layer and the medium plate and a part of the bottom plate are disposed in a first trench penetrating the first insulation layer. The bottom plate, the first patterned dielectric layer, and the medium plate constitute a first metal-insulator-metal (MIM) capacitor. The second patterned dielectric layer is disposed on the medium plate. The top plate is disposed on the second patterned dielectric layer. The medium plate, the second patterned dielectric layer, and the top plate constitute a second MIM capacitor. The bottom plate is electrically connected with the top plate.
Public/Granted literature
- US20190035674A1 INTEGRATED CIRCUIT AND MANUFACTURING METHOD THEREOF Public/Granted day:2019-01-31
Information query
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