Invention Grant
- Patent Title: Dual channel CMOS having common gate stacks
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Application No.: US15813958Application Date: 2017-11-15
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Publication No.: US10249540B2Publication Date: 2019-04-02
- Inventor: Takashi Ando , Hemanth Jagannathan , ChoongHyun Lee , Vijay Narayanan
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent Vazken Alexanian
- Main IPC: H01L29/76
- IPC: H01L29/76 ; H01L29/94 ; H01L21/8238 ; H01L21/324 ; H01L27/092 ; H01L29/06 ; H01L29/49 ; H01L29/161 ; H01L29/16 ; H01L29/10 ; H01L21/28 ; H01L21/02

Abstract:
Embodiments are directed to a method and resulting structures for a dual channel complementary metal-oxide-semiconductor (CMOS) having common gate stacks. A first semiconductor fin is formed on a substrate. A second semiconductor fin is formed adjacent to the first semiconductor fin on the substrate. An oxide layer is formed over the first and second semiconductor fins and annealed at a temperature effective to increase a germanium concentration of the second semiconductor fin. The annealing process is selective to the second semiconductor fin and does not increase a germanium concentration of the first semiconductor fin.
Public/Granted literature
- US20180337098A1 DUAL CHANNEL CMOS HAVING COMMON GATE STACKS Public/Granted day:2018-11-22
Information query
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