Invention Grant
- Patent Title: Semiconductor device package with a stress relax pattern
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Application No.: US15461465Application Date: 2017-03-16
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Publication No.: US10249573B2Publication Date: 2019-04-02
- Inventor: Ting-Feng Su , Chia-Jen Chou
- Applicant: POWERTECH TECHNOLOGY INC.
- Applicant Address: TW Hsinchu County
- Assignee: POWERTECH TECHNOLOGY INC.
- Current Assignee: POWERTECH TECHNOLOGY INC.
- Current Assignee Address: TW Hsinchu County
- Agent Winston Hsu
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L23/538 ; H01L21/56 ; H01L21/48 ; H01L23/373 ; H01L23/31

Abstract:
A semiconductor device package has a die, a pattern of dielectric material formed on an active surface of the die, a plurality of metal contacts electrically connected to the die and surrounded by the pattern, a mold compound formed around the pattern, the die and the metal contacts, and a redistribution layer formed on a grinded surface of the mold compound and electrically connected to the metal contacts. The dielectric material has a young's modulus lower than a young's modulus of the mold compound, and the dielectric material has a coefficient of thermal expansion lower than a coefficient of thermal expansion of the mold compound.
Public/Granted literature
- US20180269160A1 Semiconductor device package with a stress relax pattern Public/Granted day:2018-09-20
Information query
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