- Patent Title: Stackable semiconductor package and manufacturing method thereof
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Application No.: US15263391Application Date: 2016-09-13
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Publication No.: US10249585B2Publication Date: 2019-04-02
- Inventor: Yun-Hsin Yeh , Hung-Hsin Hsu
- Applicant: Powertech Technology Inc.
- Applicant Address: TW Hsinchu County
- Assignee: Powertech Technology Inc.
- Current Assignee: Powertech Technology Inc.
- Current Assignee Address: TW Hsinchu County
- Agency: JCIPRNET
- Priority: TW105113516A 20160429
- Main IPC: H01L21/48
- IPC: H01L21/48 ; H01L21/56 ; H01L23/49 ; H01L25/10 ; H01L23/31 ; H01L23/00 ; H01L23/498

Abstract:
A stackable semiconductor package and manufacturing method thereof are provided. The stackable semiconductor package includes carrier, first RDL, encapsulation layer, vertical interposers, second RDL, and chip. The carrier has first surface in which the first RDL and the encapsulation layer are formed thereon. The first RDL includes first pads and second pads. The encapsulation layer covers the first RDL and has outer surface. The vertical interposers are disposed in the encapsulation layer to electrically connect with the first RDL. The second RDL is formed on the outer surface to electrically connect with the vertical interposers. The carrier includes terminal holes and chip-accommodating hole. The terminal holes correspondingly expose the second pads. The chip-accommodating hole exposes the first pads. The chip is mounted on the encapsulation layer through the chip-accommodating hole to electrically connect with the first pads.
Public/Granted literature
- US20170317041A1 STACKABLE SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF Public/Granted day:2017-11-02
Information query
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