Invention Grant
- Patent Title: Semiconductor memory device including multilayer wiring layer
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Application No.: US15701499Application Date: 2017-09-12
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Publication No.: US10249626B2Publication Date: 2019-04-02
- Inventor: Shunpei Yamazaki , Yasuhiko Takemura
- Applicant: Semiconductor Energy Laboratory Co., Ltd.
- Applicant Address: JP Atsugi-shi, Kanagawa-ken
- Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee Address: JP Atsugi-shi, Kanagawa-ken
- Agency: Fish & Richardson P.C.
- Priority: JP2011-005401 20110114
- Main IPC: G11C11/24
- IPC: G11C11/24 ; H01L27/108 ; H01L21/84 ; H01L27/06 ; H01L27/12 ; H01L49/02 ; G11C5/10 ; G11C11/401 ; H01L29/786 ; G11C11/408 ; H01L23/528 ; H01L23/532

Abstract:
The memory capacity of a DRAM is enhanced. A semiconductor memory device includes a driver circuit including part of a single crystal semiconductor substrate, a multilayer wiring layer provided over the driver circuit, and a memory cell array layer provided over the multilayer wiring layer. That is, the memory cell array overlaps with the driver circuit. Accordingly, the integration degree of the semiconductor memory device can be increased as compared to the case where a driver circuit and a memory cell array are provided in the same plane of a substrate containing a singe crystal semiconductor material.
Public/Granted literature
- US20170373068A1 SEMICONDUCTOR MEMORY DEVICE Public/Granted day:2017-12-28
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