Invention Grant
- Patent Title: Structure featuring ferroelectric capacitance in interconnect level for steep sub-threshold complementary metal oxide semiconductor transistors
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Application No.: US15815326Application Date: 2017-11-16
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Publication No.: US10249630B2Publication Date: 2019-04-02
- Inventor: Takashi Ando , Karthik Balakrishnan , Pouya Hashemi , Alexander Reznicek
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Agent L. Jeffrey Kelly, Esq.
- Main IPC: H01L27/11507
- IPC: H01L27/11507 ; H01L21/8238 ; H01L27/06 ; H01L27/092 ; H01L29/06 ; H01L29/08 ; H01L49/02
Abstract:
After forming a first functional gate stack located on a first body region of a first semiconductor material portion located in a first region of a substrate and a second functional gate stack located on a second body region of a second semiconductor material portion located in a second region of the substrate, a ferroelectric gate interconnect structure is formed connecting the first functional gate stack and the second functional gate stack. The ferroelectric gate interconnect structure includes a U-shaped bottom electrode structure, a U-shaped ferroelectric material liner and a top electrode structure.
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