Invention Grant
- Patent Title: FinFET with sigma recessed source/drain and un-doped buffer layer epitaxy for uniform junction formation
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Application No.: US15808405Application Date: 2017-11-09
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Publication No.: US10249758B2Publication Date: 2019-04-02
- Inventor: Dechao Guo , Hemanth Jagannathan , Shogo Mochizuki , Gen Tsutsui , Chun-Chen Yeh
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Agent Daniel P. Morris, Esq.
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L21/02 ; H01L21/3065 ; H01L21/306 ; H01L29/66 ; H01L29/165 ; H01L29/08

Abstract:
After forming a gate structure over a semiconductor fin that extends upwards from a semiconductor substrate portion, a sigma cavity is formed within the semiconductor fin on each side of the gate structure. A semiconductor buffer region composed of an un-doped stress-generating semiconductor material is epitaxially growing from faceted surfaces of the sigma cavity. Finally, a doped semiconductor region composed of a doped stress-generating semiconductor material is formed on the semiconductor buffer region to completely fill the sigma cavity. The doped semiconductor region is formed to have substantially vertical sidewalls for formation of a uniform source/drain junction profile.
Public/Granted literature
- US20180358465A1 FINFET WITH SIGMA RECESSED SOURCE/DRAIN AND UN-DOPED BUFFER LAYER EPITAXY FOR UNIFORM JUNCTION FORMATION Public/Granted day:2018-12-13
Information query
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