Invention Grant
- Patent Title: Energy efficient, robust differential mode d-flip-flop
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Application No.: US15575611Application Date: 2016-05-23
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Publication No.: US10250236B2Publication Date: 2019-04-02
- Inventor: Sarma Vrudhula , Niranjan Kulkarni , Jinghua Yang
- Applicant: Sarma Vrudhula , Niranjan Kulkarni , Jinghua Yang
- Applicant Address: US AZ Scottsdale
- Assignee: Arizona Board of Regents on behalf of Arizona State University
- Current Assignee: Arizona Board of Regents on behalf of Arizona State University
- Current Assignee Address: US AZ Scottsdale
- Agency: Withrow & Terranova, P.L.L.C.
- International Application: PCT/US2016/033811 WO 20160523
- International Announcement: WO2016/191385 WO 20161201
- Main IPC: H03K3/037
- IPC: H03K3/037 ; H03K3/012 ; H03K3/356

Abstract:
A differential sense flip flop (DSFF) that is named the Kulkarni Vrudhula flip flop (KVFF) is disclosed. In one embodiment, the DSFF includes a differential sense amplifier and an SR latch. The differential sense amplifier includes a first amplifier branch having a first output node, a second amplifier branch having a second, a first switchable discharge path, and a second switchable discharge path. The first switchable discharge path is closed to discharge the first output node when first output node is being discharged by the first amplifier branch and the second switchable discharge path is closed to discharge the second output node when second output node is being discharged by the second amplifier branch. This prevents the output nodes from floating and increases the reliability and robustness of the DSFF.
Public/Granted literature
- US20180159512A1 ENERGY EFFICIENT, ROBUST DIFFERENTIAL MODE D-FLIP-FLOP Public/Granted day:2018-06-07
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