Invention Grant
- Patent Title: Semiconductor device and circuit arrangement using the same
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Application No.: US15091827Application Date: 2016-04-06
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Publication No.: US10250255B2Publication Date: 2019-04-02
- Inventor: Hiroshi Yanagigawa
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Koutou-ku, Tokyo
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Koutou-ku, Tokyo
- Agency: Sughrue Mion, PLLC
- Priority: JP2015-084251 20150416
- Main IPC: H03K17/687
- IPC: H03K17/687 ; H01L21/8234 ; H01L27/02 ; H01L29/78 ; H01L27/088 ; H01L29/06 ; H01L29/36 ; H03K17/06
Abstract:
A semiconductor device and a circuit arrangement are provided so as to reduce an on resistance. A first power MOS transistor and a second power MOS transistor are formed on the same semiconductor substrate. A first power MOS transistor formed in a first element formation region has a columnless structure including no columns. The second power MOS transistor formed in a second element formation region has an SJ structure including columns.
Public/Granted literature
- US20160308529A1 SEMICONDUCTOR DEVICE AND CIRCUIT ARRANGEMENT USING THE SAME Public/Granted day:2016-10-20
Information query
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