Methods and apparatuses to generate test patterns for detecting faults in an integrated circuit (IC) are described. During operation, the system receives a netlist and a layout for the IC. The system then generates a set of faults associated with the netlist to model a set of defects associated with the IC. Next, the system determines a set of likelihoods of occurrence for the set of faults based at least on a portion of the layout associated with each fault in the set of faults. The system subsequently generates a set of test patterns to target the set of faults, wherein the set of test patterns are generated based at least on the set of likelihoods of occurrence associated with the set of faults.