Invention Grant
- Patent Title: Layout pattern proximity correction through fast edge placement error prediction
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Application No.: US15367060Application Date: 2016-12-01
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Publication No.: US10254641B2Publication Date: 2019-04-09
- Inventor: Julien Mailfert , Saravanapriyan Sriraman , Mehmet Derya Tetiker
- Applicant: Lam Research Corporation
- Applicant Address: US CA Fremont
- Assignee: Lam Research Corporation
- Current Assignee: Lam Research Corporation
- Current Assignee Address: US CA Fremont
- Agency: Weaver Austin Villeneuve & Sampson LLP
- Main IPC: G03F1/36
- IPC: G03F1/36 ; G06F17/50

Abstract:
Disclosed are methods of generating a proximity-corrected design layout for photoresist to be used in an etch operation. The methods may include identifying a feature in an initial design layout, and estimating one or more quantities characteristic of an in-feature plasma flux (IFPF) within the feature during the etch operation. The methods may further include estimating a quantity characteristic of an edge placement error (EPE) of the feature by comparing the one or more quantities characteristic of the IFPF to those in a look-up table (LUT, and/or through application of a multivariate model trained on the LUT, e.g., constructed through machine learning methods (MLM)) which associates values of the quantity characteristic of EPE with values of the one or more quantities characteristics of the IFPF. Thereafter, the initial design layout may be modified based on at the determined quantity characteristic of EPE.
Public/Granted literature
- US20180157161A1 DESIGN LAYOUT PATTERN PROXIMITY CORRECTION THROUGH FAST EDGE PLACEMENT ERROR PREDICTION Public/Granted day:2018-06-07
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