Invention Grant
- Patent Title: Modifying design layer of integrated circuit (IC) using nested and non-nested fill objects
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Application No.: US15884573Application Date: 2018-01-31
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Publication No.: US10254642B2Publication Date: 2019-04-09
- Inventor: Veeresh V. Deshpande , Howard S. Landis , Arun Sankar Mampazhy , Neelima Mandloi
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Hoffman Warnick LLC
- Agent Steven J. Meyers
- Main IPC: G03F1/36
- IPC: G03F1/36 ; G03F7/20 ; G06F17/50

Abstract:
Various embodiments include approaches for modifying a design layer of an integrated circuit (IC). In some cases, an approach includes: identifying at least one empty region in a design layer used to form the IC; determining whether the at least one empty region requires a fill object; placing at least one fill object in the at least one empty region and tagging the at least one fill object in response to determining the at least one empty region requires a fill object; performing a simplified optical proximity correction (OPC) on the tagged at least one fill object and a complete OPC on the design layer; and generating a modified design layer including a corrected version of the design layer and modified fill objects after the performing of the simplified OPC on the tagged at least one fill object and the complete OPC on the design layer.
Public/Granted literature
- US20180180989A1 MODIFYING DESIGN LAYER OF INTEGRATED CIRCUIT (IC) Public/Granted day:2018-06-28
Information query