Invention Grant
- Patent Title: Regulator circuit with enhanced ripple reduction speed
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Application No.: US14840257Application Date: 2015-08-31
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Publication No.: US10254777B2Publication Date: 2019-04-09
- Inventor: Quoc Hoang Duong
- Applicant: SAMSUNG ELECTRONICS CO., LTD.
- Applicant Address: KR Suwon-si, Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si, Gyeonggi-do
- Agency: Volentine, Whitt & Francos, PLLC
- Priority: KR10-2015-0099554 20150714
- Main IPC: G05F1/575
- IPC: G05F1/575 ; H02M1/14 ; H02M1/00

Abstract:
A regulator circuit includes an OP-amp, buffer, power transistor, voltage divider, load, and feedback current generator. The OP-amp generates a first voltage signal by amplifying a difference between input and feedback voltage signals, and drives a first node as the first voltage signal. The buffer drives a second node as a second voltage signal based on the first voltage signal. The power transistor includes drain, gate and source terminals respectively connected to a supply voltage, the second node, and a third node. The voltage divider generates the feedback voltage signal by dividing an output voltage signal of the third node. The load includes a terminal connected to the third node and another terminal receiving a ground voltage. The feedback current generator provides a first feedback current corresponding to a ripple of the output voltage signal to the first node for enhancing a speed at which the ripple reduced.
Public/Granted literature
- US20170308107A9 REGULATOR CIRCUIT WITH ENHANCED RIPPLE REDUCTION SPEED Public/Granted day:2017-10-26
Information query
IPC分类: