Apparatus and methods of reducing clock path power consumption are described herein. According to one embodiment, an example apparatus includes a clock control circuit. The clock control circuit includes a command/address domain configured to selectively provide a command/address clock signal based, at least in part, on a chip select signal. The clock control circuit further includes a command domain circuit configured to selectively provide a command clock signal based, at least in part, on the chip select signal. The clock control circuit further includes a column latency domain circuit configured to selectively provide a column latency clock signal based, at least in part, on a memory command. The clock control circuit further includes a four phase domain circuit configured to selectively provide a four phase clock signal based, at least in part on the memory command.