Invention Grant
- Patent Title: Configurable and power-optimized integrated gate-driver for USB power-delivery and type-C SoCs
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Application No.: US15648036Application Date: 2017-07-12
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Publication No.: US10254820B2Publication Date: 2019-04-09
- Inventor: Anup Nayak , Ramakrishna Venigalla
- Applicant: Cypress Semiconductor Corporation
- Applicant Address: US CA San Jose
- Assignee: Cypress Semiconductor Corporation
- Current Assignee: Cypress Semiconductor Corporation
- Current Assignee Address: US CA San Jose
- Main IPC: G06F9/00
- IPC: G06F9/00 ; H01L29/76 ; H01L29/772 ; G06F1/3287 ; G06F13/38 ; G06F13/42 ; G06F1/26 ; G06F13/40
Abstract:
Techniques for power Field Effect Transistor (power-FET) gate drivers are described herein. In an example embodiment, a USB-enabled system comprises a first and second power paths and an IC controller coupled to control the first and second power paths, where the first and second power paths are external to the IC controller and the IC controller is configured to operate both an N-channel power-FET in the first power path and a P-channel power-FET in the second power path.
Public/Granted literature
- US20170351320A1 CONFIGURABLE AND POWER-OPTIMIZED INTEGRATED GATE-DRIVER FOR USB POWER-DELIVERY AND TYPE-C SOCS Public/Granted day:2017-12-07
Information query
