Invention Grant
- Patent Title: Method and apparatus for sub-page write protection
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Application No.: US14979038Application Date: 2015-12-22
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Publication No.: US10255196B2Publication Date: 2019-04-09
- Inventor: Vedvyas Shanbhogue , Christopher Bryant , Jeff Wiedemeier
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Nicholson De Vos Webster & Elliott LLP
- Main IPC: G06F12/10
- IPC: G06F12/10 ; G06F12/1045 ; G06F12/0875 ; G06F12/1027 ; G06F12/14

Abstract:
An apparatus and method for sub-page extended page table protection. For example, one embodiment of an apparatus comprises: a page miss handler to perform a page walk using a guest physical address (GPA) and to detect whether a page identified with the GPA is mapped with sub-page permissions; a sub-page control storage to store at least one GPA and other data related to a sub-page; the page miss handler to determine whether the GPA is programmed in the sub-page control storage; and the page miss handler to send a translation to a translation lookaside buffer (TLB) with a sub-page protection indication set to cause a matching of the sub-page control storage when an access matches a TLB entry with sub-page protection indication.
Public/Granted literature
- US20170177500A1 METHOD AND APPARATUS FOR SUB-PAGE WRITE PROTECTION Public/Granted day:2017-06-22
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