Invention Grant
- Patent Title: Analyzing delay variations and transition time variations for electronic circuits
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Application No.: US15067576Application Date: 2016-03-11
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Publication No.: US10255395B2Publication Date: 2019-04-09
- Inventor: Duc Huynh , Jiayong Le , Ayhan Mutlu , Peivand Tehrani
- Applicant: Synopsys, Inc.
- Applicant Address: US CA Mountain View
- Assignee: Synopsys, Inc.
- Current Assignee: Synopsys, Inc.
- Current Assignee Address: US CA Mountain View
- Agency: Fenwick & West LLP
- Main IPC: G06F9/455
- IPC: G06F9/455 ; G06F17/50

Abstract:
A system receives a circuit description and measures of intrinsic delay, intrinsic delay variation, transition time and transition time variation for each stage and determines stage delay variation of each stage. The system receives a circuit description and derate factors and determines an intrinsic delay standard deviation and a correlation coefficient. The system determines a stage delay variation of each stage based on the determined factors. The system receives parameters describing an asymmetric distribution of delay values and generates a normal distribution of delay values. The system receives measures of nominal transition time at an output and input of a wire, and transition time variation at the input of the wire and determines a transition time variation at the output of the wire. The system receives measures of an Elmore delay and a nominal delay of the wire and determines a delay variation at the output of the wire.
Public/Granted literature
- US20170262569A1 Analyzing Delay Variations and Transition Time Variations for Electronic Circuits Public/Granted day:2017-09-14
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