Invention Grant
- Patent Title: Self-aligned double patterning
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Application No.: US14869610Application Date: 2015-09-29
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Publication No.: US10256096B2Publication Date: 2019-04-09
- Inventor: Kuan-Wei Huang , Chia-Ying Lee , Ming-Chung Liang
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company
- Current Assignee: Taiwan Semiconductor Manufacturing Company
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L21/033 ; H01L21/768 ; H01L21/311
Abstract:
A semiconductor device and a method of forming the same are provided. An embodiment comprises a target layer and masking layers over the target layer. First openings are formed in the uppermost layer of the masking layers. Spacers are formed along sidewalls of the first openings, remaining first openings having a first pattern. Second openings are formed in the uppermost layer of the masking layers, the second openings having a second pattern. The first pattern and the second pattern are partially transferred to the target layer.
Public/Granted literature
- US20160020100A1 Self-Aligned Double Patterning Public/Granted day:2016-01-21
Information query
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