Invention Grant
- Patent Title: Method for fabricating a field effect transistor having a surrounding grid
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Application No.: US15938321Application Date: 2018-03-28
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Publication No.: US10256102B2Publication Date: 2019-04-09
- Inventor: Remi Coquand , Emmanuel Augendre , Shay Reboh
- Applicant: Commissariat a l'energie atomique et aux energies alternatives
- Applicant Address: FR Paris
- Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
- Current Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
- Current Assignee Address: FR Paris
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: FR1752741 20170331
- Main IPC: H01L21/285
- IPC: H01L21/285 ; H01L29/66 ; H01L29/40 ; H01L29/417 ; H01L29/423 ; H01L29/775 ; H01L29/06 ; H01L29/08 ; H01L21/02 ; H01L29/45 ; H01L29/786

Abstract:
A process for fabricating a gate-wrap-around field-effect transistor is provided, including providing a substrate surmounted with first and second nanowires extending in a same longitudinal direction and having a median portion covered by a first material, and first and second ends that are arranged on either side of the median portion, a periphery of which is covered by respective first and second dielectric spacers made of a second material that is different from the first material, the ends having exposed lateral faces; doping a portion of the first and second ends via the lateral faces; depositing an amorphous silicon alloy on the first and second lateral faces followed by crystallizing the alloy; and depositing a metal on either side of the nanowires to form first and second metal contacts that respectively make electrical contact with the doped portions of the first and second ends of the nanowires.
Public/Granted literature
- US20180301341A1 METHOD FOR FABRICATING A FIELD EFFECT TRANSISTOR HAVING A SURROUNDING GRID Public/Granted day:2018-10-18
Information query
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