Invention Grant
- Patent Title: Method of reducing overlay error in via to grid patterning
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Application No.: US15788277Application Date: 2017-10-19
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Publication No.: US10256140B2Publication Date: 2019-04-09
- Inventor: Nihar Mohanty
- Applicant: Tokyo Electron Limited
- Applicant Address: JP Tokyo
- Assignee: Tokyo Electron Limited
- Current Assignee: Tokyo Electron Limited
- Current Assignee Address: JP Tokyo
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L21/033 ; H01L21/311 ; H01L23/535

Abstract:
Techniques herein include a method of patterning a substrate that uses a self-alignment based process to align a via to odd and even trenches by using multiple different materials. Methods herein decompose or separate a via pattern into spacer side via and mandrel side via, and then sequentially access the spacer side and mandrel side respectively. With such a technique, overlay of via to grid is significantly improved. By using an additional memorization layer underneath a trench memorization layer and independently accessing the spacer side and mandrel side in the midst of a trench pattern, significant improvement in via alignment is achieved.
Public/Granted literature
- US20180114721A1 Method of Reducing Overlay Error in Via to Grid Patterning Public/Granted day:2018-04-26
Information query
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