Invention Grant
- Patent Title: Semiconductor wafer dicing crack prevention using chip peripheral trenches
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Application No.: US15444386Application Date: 2017-02-28
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Publication No.: US10256149B2Publication Date: 2019-04-09
- Inventor: Arno Zechmann , Gianmauro Pozzovivo
- Applicant: Infineon Technologies Austria AG
- Applicant Address: AT Villach
- Assignee: Infineon Technologies Austria AG
- Current Assignee: Infineon Technologies Austria AG
- Current Assignee Address: AT Villach
- Agency: Murphy, Bilak & Homiller, PLLC
- Main IPC: H01L21/78
- IPC: H01L21/78 ; H01L29/04 ; H01L23/00 ; H01L29/778 ; H01L29/06 ; H01L23/544 ; H01L29/66

Abstract:
A semiconductor base substrate having a substantially planar growth surface is provided. A first type III-V semiconductor layer is epitaxially grown on the growth surface. First and second trenches that vertically extend from an upper surface of the first type III-V semiconductor layer at least to the growth surface are formed. The first and second trenches are filled with a filler material that is different from material of the type III-V semiconductor layer. A cut that separates the first type III-V semiconductor layer and the base substrate into two discrete semiconductor chips is formed. The cut is formed in a lateral section of the first type III-V semiconductor layer that is between the first and second trenches.
Public/Granted literature
- US20180247869A1 Semiconductor Wafer Dicing Crack Prevention Using Chip Peripheral Trenches Public/Granted day:2018-08-30
Information query
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