Invention Grant
- Patent Title: Middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stack
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Application No.: US14951333Application Date: 2015-11-24
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Publication No.: US10256296B2Publication Date: 2019-04-09
- Inventor: Injo Ok , Balasubramanian Pranatharthiharan , Soon-Cheon Seo , Charan V. V. S. Surisetty
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Sherman IP LLP
- Agent Kenneth L. Sherman; Steven Laut
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L21/764 ; H01L21/762 ; H01L21/3105 ; H01L21/3213 ; H01L21/3065 ; H01L29/49 ; H01L21/768 ; H01L21/8234 ; H01L23/532 ; H01L23/535 ; H01L27/088 ; H01L23/485
Abstract:
A semiconductor structure formed based on selectively recessing a middle-of-line (MOL) oxide layer of the semiconductor structure including multiple gate stacks formed on a substrate. A cap layer of the multiple gate stacks is selectively recessed. An air-gap oxide layer introducing one or more air-gaps is deposited. Chemical-mechanical planarization (CMP) is performed on the deposited air-gap oxide layer.
Public/Granted literature
- US20170148874A1 MIDDLE-OF-LINE (MOL) CAPACITANCE REDUCTION FOR SELF-ALIGNED CONTACT IN GATE STACK Public/Granted day:2017-05-25
Information query
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