Memory devices may receive data from data processing devices for storage and processing during write operations. The received data may be accompanied by a data strobing signal that informs the memory device that data available in the bus is ready for latching. The data strobing signal may be provided via a tri-stateable or bidirectional connection and, as a result, during initialization of a write operation, the input circuitry may suffer from metastability during an initial transient period. The present application discusses methods and systems that may mitigate metastability by preventing invalid states in the input circuitry when data strobing signal is invalid or disabled. Certain embodiments determine if the data strobing signal is a valid input and, accordingly, adjust the received signal to a fixed value or to a previously received value. The use of latches and differential amplifiers to perform these functions is also discussed.