A Power-on Reset circuit is described. The Power-on Reset is formed by two comparators and a latch circuit. The Power-on Reset circuit will de-assert the reset state once the supply voltage reaches a first reference point and re-assert the reset state once the supply voltage drops below a second reference point. The Power-on Reset circuit disclosed further includes circuits to initialize properly and to ensure the regulator voltage and the bandgap voltages are stable and above the ground level voltage.