A method for making a multitude of masks for manufacturing an integrated circuit includes receiving the integrated circuit design printable using a multiple-patterning process. The design includes shapes and at least one layout conflict preventing decomposition of the design into the multitude of masks. The method further includes forming a subset of the shapes including the shapes associated with the at least one layout conflict. The method further includes categorizing the shapes of the subset into one of a multitude of topology types, generating stitch candidate solutions for the multitude of topology types, and decomposing the design into a multitude of masks. The subset of the multitude of shapes is formed by generating a first graph representative of the design, decomposing the first graph into at least three colors to form a colored graph; and identifying within the first graph, a second graph including at least one conflict edge.