A computer implemented system and method of computer implemented method of instrumentation of an electronic design comprising receiving by a computer a computer readable representation of said electronic design having at least in one part of said electronic design, an analog portion. At least one instrumented netlist is generated based at least in part upon said representation of said electronic design. At least one specification of said electronic design is received and at least one set of valid states is generated based on said at least one specification. An analog verification coverage is determined utilizing said at least one instrumented netlist.