- Patent Title: Component placement with repacking for programmable logic devices
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Application No.: US14194484Application Date: 2014-02-28
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Publication No.: US10262096B2Publication Date: 2019-04-16
- Inventor: Yinan Shen , Jun Zhao
- Applicant: Lattice Semiconductor Corporation
- Applicant Address: US OR Portland
- Assignee: Lattice Semiconductor Corporation
- Current Assignee: Lattice Semiconductor Corporation
- Current Assignee Address: US OR Portland
- Agency: Haynes and Boone, LLP
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
Systems and methods are disclosed herein to provide improved placement of components in programmable logic devices (PLDs). In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a PLD. The method also includes determining a layout comprising positions of components of the PLD configured to perform the operations. The method also includes performing a timing analysis on the layout. The method also includes selectively adjusting the positions of the components using the timing analysis. Related systems and non-transitory machine-readable mediums are also provided.
Public/Granted literature
- US20150248512A1 COMPONENT PLACEMENT WITH REPACKING FOR PROGRAMMABLE LOGIC DEVICES Public/Granted day:2015-09-03
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