Invention Grant
- Patent Title: System and method for improving scan hold-time violation and low voltage operation in sequential circuit
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Application No.: US15680198Application Date: 2017-08-17
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Publication No.: US10262723B2Publication Date: 2019-04-16
- Inventor: Matthew Berzins
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR
- Agency: Renaissance IP Law Group LLP
- Main IPC: G11C11/00
- IPC: G11C11/00 ; G11C11/417 ; H03K3/037

Abstract:
According to one general aspect, an apparatus may include a flip-flop circuit. The flip-flop circuit may include a selection circuit, a memory element circuit, a clock circuit. The selection circuit to select, as the selected input signal, between at least two input signals. The memory element circuit synchronously controlled by a clock signal, and configured to store the selected input signal. The clock circuit configured to output, at least, an earlier version of the clock signal and a later version of the clock signal. The selection circuit is configured to be synchronously controlled, at least in part, by the earlier version of the clock signal such that the selected input signal is held stable when being read by the memory element circuit.
Public/Granted literature
- US20180342287A1 SYSTEM AND METHOD FOR IMPROVING SCAN HOLD-TIME VIOLATION AND LOW VOLTAGE OPERATION IN SEQUENTIAL CIRCUIT Public/Granted day:2018-11-29
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