- Patent Title: Method of forming fine interconnection for semiconductor devices
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Application No.: US15894095Application Date: 2018-02-12
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Publication No.: US10262862B1Publication Date: 2019-04-16
- Inventor: Chiang-Lin Shih , Shing-Yih Shih
- Applicant: NANYA TECHNOLOGY CORPORATION
- Applicant Address: TW New Taipei
- Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee Address: TW New Taipei
- Agency: Muncy, Geissler, Olds & Lowe, P.C.
- Main IPC: H01L21/311
- IPC: H01L21/311 ; H01L21/033 ; H01L21/28 ; H01L21/768 ; H01L21/762

Abstract:
The present disclosure provides a method of forming fine interconnection for semiconductor devices. The method includes the following steps: A substrate is provided. A first core layer is formed over the substrate. The first core layer includes a base portion, a plurality of extending line portions extending from the base portion along a first direction, and a plurality of isolated line portions isolated from the base portion. Subsequently, a spacer is formed on the sidewalls of the first core layer. A second core layer is then formed to over the substrate. The second core layer includes a plurality of surrounding line portions surrounding the plurality of isolated line portions, and includes a plurality of enclosed line portions enclosed by the plurality of extending line portions. The spacer is removed to form a plurality of openings between the first core layer and the second core layer. The first core layer and the second core layer are alternately arranged along a second direction perpendicular to the first direction after removing the spacer.
Information query
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