Invention Grant
- Patent Title: Memory and logic device and method for manufacturing the same
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Application No.: US13852917Application Date: 2013-03-28
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Publication No.: US10263066B2Publication Date: 2019-04-16
- Inventor: Masayuki Hiroi , Takashi Sakoh
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Tokyo
- Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: McGinn I.P. Law Group, PLLC
- Priority: JP2012-099630 20120425
- Main IPC: H01L49/02
- IPC: H01L49/02 ; H01L27/108 ; H01L27/02 ; H01L23/532 ; H01L23/00
Abstract:
The present invention is directed to a semiconductor integrated circuit device that basically has a non-memory array area, a memory array area, and memory capacitors formed across lower embedded metal interconnection layers including a low-dielectric constant interlayer insulating film in the memory array area. In addition, a memory-periphery metal seal ring is provided in the lower embedded metal interconnection layers having at least the low-dielectric constant interlayer insulating film so as to surround the memory array area.
Public/Granted literature
- US20130285203A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD FOR MANUFACTURING THE SAME Public/Granted day:2013-10-31
Information query
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