Invention Grant
- Patent Title: High voltage semiconductor device
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Application No.: US15018161Application Date: 2016-02-08
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Publication No.: US10263105B2Publication Date: 2019-04-16
- Inventor: Noriyuki Iwamuro , Shinsuke Harada
- Applicant: FUJI ELECTRIC CO., LTD. , NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
- Applicant Address: JP Kawasaki-Shi, Kanagawa JP Tokyo
- Assignee: FUJI ELECTRIC CO., LTD.,NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
- Current Assignee: FUJI ELECTRIC CO., LTD.,NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
- Current Assignee Address: JP Kawasaki-Shi, Kanagawa JP Tokyo
- Agency: Rabin & Berdo, P.C.
- Priority: JP2013-165624 20130808
- Main IPC: H01L21/04
- IPC: H01L21/04 ; H01L29/04 ; H01L29/06 ; H01L29/08 ; H01L29/10 ; H01L29/12 ; H01L29/16 ; H01L29/66 ; H01L29/78 ; H01L29/739 ; H01L29/15 ; H01L31/0312

Abstract:
In an embodiment, on an n−type SiC layer on an n+-type SiC semiconductor substrate and a p+ layer selectively formed on the n−type SiC layer, a p base layer is formed on which, a p+ contact layer is selectively formed. From a surface, an n counter layer penetrates the p base layer to the n−type SiC layer. A gate electrode layer is disposed via a gate insulating film, on an exposed surface of the p base layer between the p+ contact layer and the n counter layer; and a source electrode contacts the p+ contact layer and the p base layer. In a back surface, a drain electrode is disposed. A portion of the p+ layers are joined at a region of a drain electrode side of the n counter layer, by a joining unit and a p+ layer contacts a drain electrode side of the p+ layer.
Public/Granted literature
- US20160155836A1 HIGH VOLTAGE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF Public/Granted day:2016-06-02
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