A memory test method is provided that includes the steps outlined below. The memory controller performs data-writing and data-reading on a memory module. When a quantity of read data is incorrect, a data-strobe enable signal is calibrated to perform data reading. When there is one of less than one piece of negative edge data reading content, a sampling unit is triggered. When the quantity of read data increases, the condition that the data-strobe signal is not received is determined. When the quantity does not increase, the memory controller is inspected. When there is more than one piece of read data, the burst mode setting of the memory module is inspected. When the quantity is correct and the content is not correct, a transmission circuit setting and the sampling unit are inspected. When the quantity and the content are correct, the test flow is terminated.