Invention Grant
- Patent Title: Method for manufacturing SiC epitaxial wafer and SiC epitaxial wafer
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Application No.: US15329363Application Date: 2015-06-19
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Publication No.: US10269554B2Publication Date: 2019-04-23
- Inventor: Yuzo Sasaki , Susumu Sugano
- Applicant: SHOWA DENKO K.K.
- Applicant Address: JP Tokyo
- Assignee: SHOWA DENKO K.K.
- Current Assignee: SHOWA DENKO K.K.
- Current Assignee Address: JP Tokyo
- Agency: Sughrue Mion, PLLC
- Priority: JP2014-153289 20140728
- International Application: PCT/JP2015/067765 WO 20150619
- International Announcement: WO2016/017319 WO 20160204
- Main IPC: C30B25/02
- IPC: C30B25/02 ; H01L21/02 ; B24B9/00 ; C30B25/20 ; C30B29/36 ; B24B9/06 ; B24D3/06 ; B24D3/28 ; C30B33/00 ; H01L29/16 ; H01L29/34 ; C23C16/02 ; C23C16/32 ; C30B25/18 ; H01L29/04
Abstract:
In order to reduce edge defects efficiently and sufficiently, a method for manufacturing a SiC epitaxial wafer according to the present invention is a method for manufacturing a SiC epitaxial wafer that forms a SiC epitaxial layer on top of a SiC single crystal substrate having an off angle, and includes a rough polishing step for subjecting an outer circumferential edge on a starting side of step-flow growth in the SiC single crystal substrate to rough polishing before forming the SiC epitaxial layer; and a final polishing step for further polishing for finish.
Public/Granted literature
- US20170221697A1 METHOD FOR MANUFACTURING SIC EPITAXIAL WAFER AND SIC EPITAXIAL WAFER Public/Granted day:2017-08-03
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