Invention Grant
- Patent Title: Wafer level flat no-lead semiconductor packages and methods of manufacture
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Application No.: US15883625Application Date: 2018-01-30
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Publication No.: US10269609B2Publication Date: 2019-04-23
- Inventor: Darrell D. Truhitte , James P. Letterman, Jr.
- Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- Applicant Address: US AZ Phoenix
- Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- Current Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- Current Assignee Address: US AZ Phoenix
- Agency: IPTechLaw
- Main IPC: H01L21/78
- IPC: H01L21/78 ; H01L23/495 ; H01L23/31 ; H01L21/683 ; H01L21/56 ; H01L21/48 ; H01L23/00 ; H01L23/36 ; H01L25/065 ; H01L25/10

Abstract:
Methods of manufacturing semiconductor packages. Implementations may include: providing a substrate with a first side, a second side, and a thickness; forming a plurality of pads on the first side of the substrate; and applying die attach material to the plurality of pads. The method may include bonding a wafer including a plurality of semiconductor die to the substrate at one or more die pads included in each die. The method may also include singulating the plurality of semiconductor die, overmolding the plurality of semiconductor die and the first side of the substrate with an overmold material, and removing the substrate to expose the plurality of pads and to form a plurality of semiconductor packages coupled together through the overmold material. The method also may include singulating the plurality of semiconductor packages to separate them.
Public/Granted literature
- US20180174881A1 WAFER LEVEL FLAT NO-LEAD SEMICONDUCTOR PACKAGES AND METHODS OF MANUFACTURE Public/Granted day:2018-06-21
Information query
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