Invention Grant
- Patent Title: Stacked integrated circuits with redistribution lines
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Application No.: US15269431Application Date: 2016-09-19
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Publication No.: US10269768B2Publication Date: 2019-04-23
- Inventor: Cheng-Ying Ho , Jeng-Shyan Lin , Wen-I Hsu , Feng-Chi Hung , Dun-Nian Yaung , Ying-Ling Tsai
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L21/768 ; H01L23/522 ; H01L23/00 ; H01L25/00 ; H01L23/48

Abstract:
A method includes bonding a first wafer to a second wafer, with a first plurality of dielectric layers in the first wafer and a second plurality of dielectric layers in the second wafer bonded between a first substrate of the first wafer and a second substrate in the second wafer. A first opening is formed in the first substrate, and the first plurality of dielectric layers and the second wafer are etched through the first opening to form a second opening. A metal pad in the second plurality of dielectric layers is exposed to the second opening. A conductive plug is formed extending into the first and the second openings.
Public/Granted literature
- US20170005076A1 Stacked Integrated Circuits with Redistribution Lines Public/Granted day:2017-01-05
Information query
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