- Patent Title: Vertical gate semiconductor device with steep subthreshold slope
-
Application No.: US15605983Application Date: 2017-05-26
-
Publication No.: US10269800B2Publication Date: 2019-04-23
- Inventor: Hung-Li Chiang , Szu-Wei Huang , Chih-Chieh Yeh , Yee-Chia Yeo
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: McClure, Qualey & Rodack, LLP
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L29/06 ; H01L29/78 ; H01L23/528 ; H01L21/8238 ; H01L21/8234

Abstract:
A semiconductor device includes a substrate, a well on the substrate and an FFT on the well. The FET includes a first source/drain, a vertical channel layer, a gate structure, a second source/drain and a body structure. The first source/drain is on the well. The vertical channel layer extends form the first source/drain. The first gate structure surrounds a first portion of sidewalls of the vertical channel layer. The second source/drain is on the vertical channel layer. The body structure is in physical contact with the vertical channel layer. The body structure and the vertical channel layer constitute a bipolar device.
Public/Granted literature
- US20180342516A1 VERTICAL GATE SEMICONDUCTOR DEVICE WITH STEEP SUBTHRESHOLD SLOPE Public/Granted day:2018-11-29
Information query
IPC分类: