Invention Grant
- Patent Title: Method for producing a semiconductor device with self-aligned internal spacers
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Application No.: US15837217Application Date: 2017-12-11
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Publication No.: US10269930B2Publication Date: 2019-04-23
- Inventor: Shay Reboh , Emmanuel Augendre , Remi Coquand
- Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
- Applicant Address: FR Paris
- Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
- Current Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
- Current Assignee Address: FR Paris
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: FR1662532 20161215
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L29/66 ; H01L29/06 ; H01L29/10 ; H01L29/423 ; H01L29/786 ; H01L29/161

Abstract:
Method for producing a semiconductor device, comprising: producing a stack including a first crystalline semiconductor portion intended to form a channel and arranged on at least one second portion which can be selectively etched vis-à-vis the first portion, producing a dummy gate and external spacers, etching the stack, a remaining part of the stack under the dummy gate and the external spacers being conserved, producing source/drain by epitaxy from the remaining part of the stack; removing the dummy gate and the second portion, oxidizing portions of the source/drain from the parts of the source/drain revealed by the removal of the second portion, forming internal spacers, producing a gate electrically insulated from the source/drain by the external and internal spacers.
Public/Granted literature
- US20180175166A1 METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE WITH SELF-ALIGNED INTERNAL SPACERS Public/Granted day:2018-06-21
Information query
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