Invention Grant
- Patent Title: Reduced resistance source and drain extensions in vertical field effect transistors
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Application No.: US15850891Application Date: 2017-12-21
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Publication No.: US10269957B2Publication Date: 2019-04-23
- Inventor: Peng Xu , Chun W. Yeung , Chen Zhang
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Tutunjian & Bitetto, P.C.
- Agent Vazken Alexanian
- Main IPC: H01L21/02
- IPC: H01L21/02 ; H01L29/08 ; H01L29/78 ; H01L29/66 ; H01L21/311

Abstract:
Semiconductor devices and methods of forming the same include forming a bottom source/drain region in a semiconductor substrate under a semiconductor fin. First charged spacers are formed on sidewalls of the semiconductor fin. A gate stack is formed on the fin, over the first charged spacers. Second charged spacers are formed on sidewalls of the fin above the gate stack. The fin is recessed to a height below a top level of the second charged spacers. A top source/drain region is grown from the recessed fin.
Public/Granted literature
- US20180197990A1 REDUCED RESISTANCE SOURCE AND DRAIN EXTENSIONS IN VERTICAL FIELD EFFECT TRANSISTORS Public/Granted day:2018-07-12
Information query
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