Invention Grant
- Patent Title: Low leakage ReRAM FPGA configuration cell
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Application No.: US15375014Application Date: 2016-12-09
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Publication No.: US10270451B2Publication Date: 2019-04-23
- Inventor: John L. McCollum , Esmat Z. Hamdy
- Applicant: Microsemi SoC Corporation
- Applicant Address: US CA San Jose
- Assignee: Microsemi SoC Corporation
- Current Assignee: Microsemi SoC Corporation
- Current Assignee Address: US CA San Jose
- Agency: Glass and Associates
- Agent Kenneth D'Alessandro; Kenneth Glass
- Main IPC: G11C13/00
- IPC: G11C13/00 ; H03K19/094 ; H01L27/24 ; H01L23/00 ; H03K19/177 ; H01L45/00
Abstract:
A low-leakage resistive random access memory cell includes a complementary pair of bit lines and a switch node. A first ReRAM device is connected to a first one of the bit lines. A p-channel transistor has a source connected to the ReRAM device, a drain connected to the switch node, and a gate connected to a bias potential. A second ReRAM device is connected to a second one of the bit lines. An n-channel transistor has a source connected to the ReRAM device a drain connected to the switch node, and a gate connected to a bias potential.
Public/Granted literature
- US20170179959A1 LOW LEAKAGE ReRAM FPGA CONFIGURATION CELL Public/Granted day:2017-06-22
Information query
