Invention Grant
- Patent Title: Semiconductor device and diagnostic test method for both single-point and latent faults using first and second scan tests
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Application No.: US15547440Application Date: 2015-06-18
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Publication No.: US10281525B2Publication Date: 2019-05-07
- Inventor: Yoichi Maeda , Jun Matsushima , Takayuki Suzuki
- Applicant: Renesas Electric Corporation
- Applicant Address: JP Tokyo
- Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: McGinn IP Law Group, PLLC
- International Application: PCT/JP2015/003047 WO 20150618
- International Announcement: WO2016/203505 WO 20161222
- Main IPC: G01R31/3177
- IPC: G01R31/3177 ; G01R31/3185 ; G01R31/317

Abstract:
A semiconductor device (1) according to the present invention includes a circuit to be tested (2) having a scan chain, and a first test control device (3) and a second test control device (4) that perform a scan test of the circuit to be tested by using the scan chain. The second test control device (4) performs a second scan test of the circuit to be tested (2), the circuit to be tested (2) gives the first test control device (3) an instruction to perform a first scan test after the second scan test is performed, and the first test control device (3) performs a first scan test of the circuit to be tested (2) in response to an instruction from the circuit to be tested (2).
Public/Granted literature
- US20180180672A1 SEMICONDUCTOR DEVICE AND DIAGNOSTIC TEST METHOD Public/Granted day:2018-06-28
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